//-----------------------------------------------------
// Design Name : 
// File Name : 
// Function : 
//-----------------------------------------------------
module InstructionMemory #(parameter WIDTH = 16, RAM_ADDR_BITS = 16)
(
	address, 
	instruction,
	clk
); 
// Input Ports 
input [15:0] address;
input clk;
// Output Ports 
output [15:0] instruction;

// Input Ports Data Type  
wire [15:0] address;

// Output Ports Data Type 
reg [15:0] instruction;

reg [WIDTH-1:0] cr16_ram [(2**RAM_ADDR_BITS)-1:0];
// Implementation
initial

$readmemh("firmware.dat", cr16_ram);

always@(posedge clk)
         instruction <= cr16_ram[address];
endmodule 